: The introduction of Flow Control Unit (FLIT) based encoding allows for the fixed-size packets required by PAM4 and the new error correction mechanisms.
| Application | Why PCIe 6.0 is needed | |-------------|------------------------| | AI/ML accelerators | Massive inter-GPU and GPU-CPU bandwidth | | 400 GbE network cards | Match network line rates without bottlenecks | | CXL (Compute Express Link) 3.0 | CXL is built on PCIe 6.0 physical/logical layers | | Automotive (ASIL-B, ASIL-D) | FEC and CRC improve reliability for autonomous driving | | NVMe SSDs | Next-generation SSDs surpassing 32 GB/s | pci express base specification revision 60 pdf
The is not merely an incremental update; it is a fundamental re-architecture of how the most popular interconnect on earth operates. By shifting to PAM4 signaling and FLIT mode with FEC , PCIe 6.0 abandons a 20-year signaling paradigm to achieve 64 GT/s. : The introduction of Flow Control Unit (FLIT)
If you are designing the next storage controller or network interface card (NIC), the PHY layer has changed dramatically. You need the spec to implement the PAM4 SerDes (Serializer/Deserializer) and the dedicated FEC logic. If you are designing the next storage controller
| Feature | PCIe 5.0 (Gen 5) | PCIe 6.0 (Gen 6) | | :--- | :--- | :--- | | | 32 GT/s | 64 GT/s | | Bandwidth (x16) | ~64 GB/s (approx. 128 GB/s bi-directional) | ~128 GB/s (approx. 256 GB/s bi-directional) | | Encoding Scheme | 128b/130b (NRZ) | PAM4 (with FEC) | | Packet Format | Variable size (TLP/ DLLP) | Fixed-size FLIT (256 bytes) | | Power Management | L1 substates | L0p (Per-lane power down) | | Target Latency | Standard | Sub-Ins latency (via FLIT) |
Instead of two voltage levels, PAM4 uses four distinct levels: